35 #define QQQdialect MPLABX 49 #undef QQQMULTIPROCESSEXH 52 #define qqqMaxBranchDepth 20 53 #define QQQstructbitmap 65 #undef QQQTEMPLATEONLY 67 #define QQQUPLOADATEND 69 #undef QQQASHLINGVITRA 71 #define qqqbitmapint unsigned int 73 #undef QQQTIC2XSERIALIO 75 #undef QQQCOMPRESSED_EXH 82 #define man_59zzopen zzopen 84 #define man_59zqqzqz1 zqqzqz1 87 #define FILEPOINT FILE * f, 88 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 105 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 108 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 109 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 117 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 118 #ifndef LDRA_VOID_FUNC 119 #define LDRA_VOID_FUNC 122 #if defined(QQQMAINFL) 145 #ifdef QQQ_KEEPCOMMENTS 153 #if !defined(QQQSUPPRESS_UNDEF) 159 #undef QQQHITMAP_STORAGE 161 #define qqnull_params void 162 #define QQQ_PROTOTYPE_DEF 164 #undef QQ_ANSI_PROTOTYPE 166 #define QQ_ANSI_PROTOTYPE 1 169 #define QQ_ANSI_PROTOTYPE 1 175 #define ELEMENT(N) qqqbitmapint element##N; 177 #include "man_59zbelem.def" 181 #define ELEMENT(N) 0, 183 #include "man_59zbelem.def" 261 #ifndef _SYSTEM_CONFIG_H 262 #define _SYSTEM_CONFIG_H 281 #define SYS_VERSION_STR "2.06" 282 #define SYS_VERSION 20600 286 #define SYS_CLK_FREQ 200000000ul 287 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 288 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 289 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 290 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 291 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 292 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 293 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 294 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 295 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 297 #define SYS_PORT_A_ANSEL 0x3F00 298 #define SYS_PORT_A_TRIS 0xFFED 299 #define SYS_PORT_A_LAT 0x0010 300 #define SYS_PORT_A_ODC 0x0000 301 #define SYS_PORT_A_CNPU 0x0020 302 #define SYS_PORT_A_CNPD 0x0000 303 #define SYS_PORT_A_CNEN 0x0021 304 #define SYS_PORT_B_ANSEL 0x10C8 305 #define SYS_PORT_B_TRIS 0x91FF 306 #define SYS_PORT_B_LAT 0x0000 307 #define SYS_PORT_B_ODC 0x0000 308 #define SYS_PORT_B_CNPU 0x0000 309 #define SYS_PORT_B_CNPD 0x0000 310 #define SYS_PORT_B_CNEN 0x0000 311 #define SYS_PORT_C_ANSEL 0xCFE1 312 #define SYS_PORT_C_TRIS 0xFFFF 313 #define SYS_PORT_C_LAT 0x0000 314 #define SYS_PORT_C_ODC 0x0000 315 #define SYS_PORT_C_CNPU 0x0000 316 #define SYS_PORT_C_CNPD 0x0000 317 #define SYS_PORT_C_CNEN 0x0000 318 #define SYS_PORT_D_ANSEL 0xC100 319 #define SYS_PORT_D_TRIS 0xFFFF 320 #define SYS_PORT_D_LAT 0x0000 321 #define SYS_PORT_D_ODC 0x0000 322 #define SYS_PORT_D_CNPU 0x0000 323 #define SYS_PORT_D_CNPD 0x0000 324 #define SYS_PORT_D_CNEN 0x0000 325 #define SYS_PORT_E_ANSEL 0xFC00 326 #define SYS_PORT_E_TRIS 0xFDFF 327 #define SYS_PORT_E_LAT 0x0000 328 #define SYS_PORT_E_ODC 0x0000 329 #define SYS_PORT_E_CNPU 0x0000 330 #define SYS_PORT_E_CNPD 0x0000 331 #define SYS_PORT_E_CNEN 0x0000 332 #define SYS_PORT_F_ANSEL 0xCEC0 333 #define SYS_PORT_F_TRIS 0xEFFF 334 #define SYS_PORT_F_LAT 0x0000 335 #define SYS_PORT_F_ODC 0x0000 336 #define SYS_PORT_F_CNPU 0x0000 337 #define SYS_PORT_F_CNPD 0x0000 338 #define SYS_PORT_F_CNEN 0x0000 339 #define SYS_PORT_G_ANSEL 0x8CBC 340 #define SYS_PORT_G_TRIS 0xDFFF 341 #define SYS_PORT_G_LAT 0x0000 342 #define SYS_PORT_G_ODC 0x0000 343 #define SYS_PORT_G_CNPU 0x0000 344 #define SYS_PORT_G_CNPD 0x0000 345 #define SYS_PORT_G_CNEN 0x0000 346 #define SYS_PORT_H_ANSEL 0x0070 347 #define SYS_PORT_H_TRIS 0xB3FB 348 #define SYS_PORT_H_LAT 0x0000 349 #define SYS_PORT_H_ODC 0x0000 350 #define SYS_PORT_H_CNPU 0x0000 351 #define SYS_PORT_H_CNPD 0x0000 352 #define SYS_PORT_H_CNEN 0x0000 353 #define SYS_PORT_J_ANSEL 0x0000 354 #define SYS_PORT_J_TRIS 0x8B7F 355 #define SYS_PORT_J_LAT 0x0080 356 #define SYS_PORT_J_ODC 0x0000 357 #define SYS_PORT_J_CNPU 0x0000 358 #define SYS_PORT_J_CNPD 0x0000 359 #define SYS_PORT_J_CNEN 0x0800 360 #define SYS_PORT_K_ANSEL 0xFF00 361 #define SYS_PORT_K_TRIS 0xFFFF 362 #define SYS_PORT_K_LAT 0x0000 363 #define SYS_PORT_K_ODC 0x0000 364 #define SYS_PORT_K_CNPU 0x0000 365 #define SYS_PORT_K_CNPD 0x0000 366 #define SYS_PORT_K_CNEN 0x0000 370 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 371 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 372 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 373 #define SYS_TMR_FREQUENCY 1000 374 #define SYS_TMR_FREQUENCY_TOLERANCE 10 375 #define SYS_TMR_UNIT_RESOLUTION 10000 376 #define SYS_TMR_CLIENT_TOLERANCE 10 377 #define SYS_TMR_INTERRUPT_NOTIFICATION false 383 #define DRV_IC_DRIVER_MODE_STATIC 386 #define DRV_SPI_NUMBER_OF_MODULES 6 389 #define DRV_SPI_POLLED 1 390 #define DRV_SPI_ISR 0 391 #define DRV_SPI_MASTER 1 392 #define DRV_SPI_SLAVE 0 394 #define DRV_SPI_EBM 1 395 #define DRV_SPI_8BIT 1 396 #define DRV_SPI_16BIT 1 397 #define DRV_SPI_32BIT 0 398 #define DRV_SPI_DMA 0 400 #define DRV_SPI_INSTANCES_NUMBER 3 401 #define DRV_SPI_CLIENTS_NUMBER 3 402 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 404 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 405 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 406 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 407 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 408 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 409 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 410 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 411 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 412 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 413 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 414 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 415 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 416 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 417 #define DRV_SPI_BAUD_RATE_IDX0 1000000 418 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 419 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 420 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 421 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 422 #define DRV_SPI_QUEUE_SIZE_IDX0 10 423 #define DRV_SPI_RESERVED_JOB_IDX0 1 425 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 426 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 427 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 428 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 429 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 430 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 431 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 432 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 433 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 434 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 435 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 436 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 437 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 438 #define DRV_SPI_BAUD_RATE_IDX1 1000000 439 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 440 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 441 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 442 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 443 #define DRV_SPI_QUEUE_SIZE_IDX1 10 444 #define DRV_SPI_RESERVED_JOB_IDX1 1 446 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 447 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 448 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 449 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 450 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 451 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 452 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 453 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 454 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 455 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 456 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 457 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 458 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 459 #define DRV_SPI_BAUD_RATE_IDX2 500000 460 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 461 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 462 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 463 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 464 #define DRV_SPI_QUEUE_SIZE_IDX2 10 465 #define DRV_SPI_RESERVED_JOB_IDX2 1 467 #define DRV_TMR_INTERRUPT_MODE true 469 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 470 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 471 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 472 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 473 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 474 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 475 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 476 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 477 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 478 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 479 #define DRV_TMR_POWER_STATE_IDX0 480 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 481 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 482 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 483 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 484 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 485 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 486 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 487 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 488 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 489 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 490 #define DRV_TMR_POWER_STATE_IDX1 492 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 493 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 494 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 495 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 496 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 497 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 498 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 499 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 500 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 501 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 502 #define DRV_TMR_POWER_STATE_IDX2 504 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 505 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 506 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 507 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 508 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 509 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 510 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 511 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 512 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 513 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 514 #define DRV_TMR_POWER_STATE_IDX3 516 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 517 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 518 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 519 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 520 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 521 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 522 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 523 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 524 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 525 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 526 #define DRV_TMR_POWER_STATE_IDX4 530 #define DRV_USART_INSTANCES_NUMBER 1 531 #define DRV_USART_CLIENTS_NUMBER 1 532 #define DRV_USART_INTERRUPT_MODE false 533 #define DRV_USART_BYTE_MODEL_SUPPORT true 534 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 535 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 543 #define DRV_USBHS_DEVICE_SUPPORT true 545 #define DRV_USBHS_HOST_SUPPORT false 547 #define DRV_USBHS_INSTANCES_NUMBER 1 549 #define DRV_USBHS_INTERRUPT_MODE true 551 #define DRV_USBHS_ENDPOINTS_NUMBER 2 554 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 556 #define USB_DEVICE_INSTANCES_NUMBER 1 558 #define USB_DEVICE_EP0_BUFFER_SIZE 64 560 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 568 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 569 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 570 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 571 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 572 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 574 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 575 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 576 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 577 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 578 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 580 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 581 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 582 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 583 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 584 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 586 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 587 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 588 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 589 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 590 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 592 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 593 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 594 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 595 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 596 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 598 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 599 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 600 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 601 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 602 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 604 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 605 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 606 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 607 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 608 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 610 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 611 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 612 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 613 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 614 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 616 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 617 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 618 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 619 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 620 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 622 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 623 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 624 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 625 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 626 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 628 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 629 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 630 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 631 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 632 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 634 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 635 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 636 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 637 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 638 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 640 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 641 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 642 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 643 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 644 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 646 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 647 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 648 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 649 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 650 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 652 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 653 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 654 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 655 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 656 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 658 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 659 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 660 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 661 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 662 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 664 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 665 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 666 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 667 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 668 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 670 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 671 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 672 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 673 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 674 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 676 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 677 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 678 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 679 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 680 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 682 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 684 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 686 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 688 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 690 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 692 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 694 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 696 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 698 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 700 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 702 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 704 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 706 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 708 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 710 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 712 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 714 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 715 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 716 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 717 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 718 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 719 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 720 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 763 #ifndef _SYS_DEFINITIONS_H 764 #define _SYS_DEFINITIONS_H 773 #include "system/common/sys_common.h" 774 #include "system/common/sys_module.h" 819 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 858 #ifndef _DRV_COMMON_H 859 #define _DRV_COMMON_H 961 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 971 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 981 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1037 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1048 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1063 #define _PLIB_UNSUPPORTED 1071 #include "system/common/sys_module.h" 1083 #define DRV_IC_INDEX_0 0 1084 #define DRV_IC_INDEX_1 1 1085 #define DRV_IC_INDEX_2 2 1086 #define DRV_IC_INDEX_3 3 1087 #define DRV_IC_INDEX_4 4 1088 #define DRV_IC_INDEX_5 5 1089 #define DRV_IC_INDEX_6 6 1090 #define DRV_IC_INDEX_7 7 1091 #define DRV_IC_INDEX_8 8 1092 #define DRV_IC_INDEX_9 9 1093 #define DRV_IC_INDEX_10 10 1094 #define DRV_IC_INDEX_11 11 1095 #define DRV_IC_INDEX_12 12 1096 #define DRV_IC_INDEX_13 13 1097 #define DRV_IC_INDEX_14 14 1098 #define DRV_IC_INDEX_15 15 1130 const SYS_MODULE_INDEX index ,
1131 const SYS_MODULE_INIT *
const init ) ;
1153 const SYS_MODULE_INDEX drvIndex ,
1198 const SYS_MODULE_INDEX drvIndex ,
1331 #ifndef _DRV_IC_STATIC_H 1332 #define _DRV_IC_STATIC_H 1333 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1334 #define DRV_IC_Close( handle ) 1373 #include "system/devcon/sys_devcon.h" 1374 #include "system/clk/sys_clk.h" 1375 #include "system/int/sys_int.h" 1376 #include "system/tmr/sys_tmr.h" 1418 #ifndef _DRV_ADC_STATIC_H 1419 #define _DRV_ADC_STATIC_H 1420 #include <stdbool.h> 1421 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1422 #include "peripheral/adchs/plib_adchs.h" 1423 #include "peripheral/int/plib_int.h" 1463 uint8_t bufIndex ) ;
1467 uint8_t bufIndex ) ;
1517 #ifndef _DRV_TMR_STATIC_H 1518 #define _DRV_TMR_STATIC_H 1567 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1568 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1569 #include "peripheral/tmr/plib_tmr.h" 1605 #ifndef _TMR_DEFINITIONS_PIC32M_H 1606 #define _TMR_DEFINITIONS_PIC32M_H 1664 #include "system/int/sys_int.h" 1665 #include "system/clk/sys_clk.h" 1684 #define DRV_TMR_INDEX_0 0 1685 #define DRV_TMR_INDEX_1 1 1686 #define DRV_TMR_INDEX_2 2 1687 #define DRV_TMR_INDEX_3 3 1688 #define DRV_TMR_INDEX_4 4 1689 #define DRV_TMR_INDEX_5 5 1690 #define DRV_TMR_INDEX_6 6 1691 #define DRV_TMR_INDEX_7 7 1692 #define DRV_TMR_INDEX_8 8 1693 #define DRV_TMR_INDEX_9 9 1694 #define DRV_TMR_INDEX_10 10 1695 #define DRV_TMR_INDEX_11 11 1706 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1791 uint32_t dividerMin ;
1793 uint32_t dividerMax ;
1796 uint32_t dividerStep ;
1812 SYS_MODULE_INIT moduleInit ;
1814 TMR_MODULE_ID tmrId ;
1818 TMR_PRESCALE prescale ;
1822 INT_SOURCE interruptSource ;
1830 bool asyncWriteEnable ;
1845 uint32_t alarmCount ) ;
1907 const SYS_MODULE_INDEX drvIndex ,
1908 const SYS_MODULE_INIT *
const init ) ;
1948 SYS_MODULE_OBJ
object ) ;
1995 SYS_MODULE_OBJ
object ) ;
2029 SYS_MODULE_OBJ
object ) ;
2083 const SYS_MODULE_INDEX index ,
2184 uint32_t counterPeriod ) ;
2674 TMR_PRESCALE preScale ) ;
2914 #ifndef _DRV_TMR_DEPRECATED_H 2915 #define _DRV_TMR_DEPRECATED_H 2956 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3020 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3085 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3144 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3205 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3264 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3325 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3355 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3387 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3418 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3450 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3512 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3577 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3594 #include "peripheral/tmr/plib_tmr.h" 3595 #include "peripheral/int/plib_int.h" 3597 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3599 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3601 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3603 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3622 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3628 static inline SYS_STATUS
3631 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3642 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3653 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3663 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3672 TMR_PRESCALE prescale ) ;
3703 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3732 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3738 static inline SYS_STATUS
3741 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3752 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3763 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3773 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3782 TMR_PRESCALE prescale ) ;
3813 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3842 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3848 static inline SYS_STATUS
3851 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3862 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3873 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3883 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3892 TMR_PRESCALE prescale ) ;
3923 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3952 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3958 static inline SYS_STATUS
3961 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3972 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3983 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3993 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4002 TMR_PRESCALE prescale ) ;
4033 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4062 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4068 static inline SYS_STATUS
4071 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4082 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4093 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4103 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4112 TMR_PRESCALE prescale ) ;
4143 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4162 #include "peripheral/int/plib_int.h" 4204 #ifndef _DRV_PMP_STATIC_H 4205 #define _DRV_PMP_STATIC_H 4206 #include "peripheral/pmp/plib_pmp.h" 4221 PMP_DATA_WAIT_STATES dataWait ,
4222 PMP_STROBE_WAIT_STATES strobeWait ,
4223 PMP_DATA_HOLD_STATES dataHold ) ;
4278 #ifndef _DRV_USART_STATIC_H 4279 #define _DRV_USART_STATIC_H 4318 #ifndef _DRV_USART_STATIC_LOCAL_H 4319 #define _DRV_USART_STATIC_LOCAL_H 4326 #include <stdbool.h> 4363 #ifndef _DRV_USART_H 4364 #define _DRV_USART_H 4404 #ifndef _DRV_USART_DEFINITIONS_H 4405 #define _DRV_USART_DEFINITIONS_H 4411 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4412 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4449 #ifndef _PLIB_USART_H 4450 #define _PLIB_USART_H 4493 #ifndef _USART_PROCESSOR_H 4494 #define _USART_PROCESSOR_H 4503 #include <stdbool.h> 4504 #error "No Processor Family specified" 4548 USART_MODULE_ID index ) ;
4578 USART_MODULE_ID index ) ;
4610 USART_MODULE_ID index ) ;
4644 USART_MODULE_ID index ,
4645 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4674 USART_BRG_CLOCK_SOURCE
4676 USART_MODULE_ID index ) ;
4730 USART_MODULE_ID index ) ;
4760 USART_MODULE_ID index ) ;
4789 USART_MODULE_ID index ) ;
4821 USART_MODULE_ID index ) ;
4852 USART_MODULE_ID index ) ;
4894 USART_MODULE_ID index ) ;
4927 USART_MODULE_ID index ) ;
4959 USART_MODULE_ID index ) ;
5000 USART_MODULE_ID index ,
5001 uint32_t clockFrequency ,
5002 uint32_t baudRate ) ;
5043 USART_MODULE_ID index ,
5044 uint32_t clockFrequency ,
5045 uint32_t baudRate ) ;
5078 USART_MODULE_ID index ,
5079 int32_t clockFrequency ) ;
5114 USART_MODULE_ID index ,
5149 USART_MODULE_ID index ) ;
5184 USART_MODULE_ID index ,
5219 USART_MODULE_ID index ) ;
5251 USART_MODULE_ID index ) ;
5285 USART_MODULE_ID index ) ;
5318 USART_MODULE_ID index ) ;
5351 USART_MODULE_ID index ) ;
5385 USART_MODULE_ID index ,
5430 USART_MODULE_ID index ) ;
5464 USART_MODULE_ID index ) ;
5500 USART_MODULE_ID index ) ;
5537 USART_MODULE_ID index ,
5577 USART_MODULE_ID index ) ;
5615 USART_MODULE_ID index ) ;
5650 USART_MODULE_ID index ) ;
5684 USART_MODULE_ID index ) ;
5718 USART_MODULE_ID index ) ;
5751 USART_MODULE_ID index ) ;
5783 USART_MODULE_ID index ) ;
5815 USART_MODULE_ID index ) ;
5848 USART_MODULE_ID index ) ;
5882 USART_MODULE_ID index ) ;
5911 USART_MODULE_ID index ) ;
5940 USART_MODULE_ID index ) ;
5972 USART_MODULE_ID index ) ;
6004 USART_MODULE_ID index ) ;
6034 USART_MODULE_ID index ) ;
6064 USART_MODULE_ID index ) ;
6093 USART_MODULE_ID index ) ;
6122 USART_MODULE_ID index ) ;
6156 USART_MODULE_ID index ,
6157 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6189 USART_MODULE_ID index ,
6190 USART_RECEIVE_INTR_MODE interruptMode ) ;
6223 USART_MODULE_ID index ,
6224 USART_LINECONTROL_MODE dataFlowConfig ) ;
6257 USART_MODULE_ID index ,
6258 USART_HANDSHAKE_MODE handshakeConfig ) ;
6291 USART_MODULE_ID index ,
6322 USART_MODULE_ID index ) ;
6351 USART_MODULE_ID index ) ;
6382 USART_MODULE_ID index ) ;
6413 USART_MODULE_ID index ) ;
6443 USART_MODULE_ID index ) ;
6475 USART_MODULE_ID index ,
6476 USART_OPERATION_MODE operationmode ) ;
6506 USART_MODULE_ID index ) ;
6539 USART_MODULE_ID index ) ;
6568 USART_MODULE_ID index ) ;
6598 USART_MODULE_ID index ) ;
6634 USART_MODULE_ID index ) ;
6685 USART_MODULE_ID index ,
6688 bool wakeFromSleep ,
6733 USART_MODULE_ID index ,
6734 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6735 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6736 USART_OPERATION_MODE operationMode ) ;
6782 USART_MODULE_ID index ,
6783 uint32_t systemClock ,
6829 USART_MODULE_ID index ) ;
6850 USART_MODULE_ID index ) ;
6871 USART_MODULE_ID index ) ;
6905 USART_MODULE_ID index ) ;
6932 USART_MODULE_ID index ) ;
6958 USART_MODULE_ID index ) ;
6985 USART_MODULE_ID index ) ;
7011 USART_MODULE_ID index ) ;
7036 USART_MODULE_ID index ) ;
7062 USART_MODULE_ID index ) ;
7087 USART_MODULE_ID index ) ;
7113 USART_MODULE_ID index ) ;
7138 USART_MODULE_ID index ) ;
7164 USART_MODULE_ID index ) ;
7191 USART_MODULE_ID index ) ;
7217 USART_MODULE_ID index ) ;
7243 USART_MODULE_ID index ) ;
7270 USART_MODULE_ID index ) ;
7297 USART_MODULE_ID index ) ;
7324 USART_MODULE_ID index ) ;
7350 USART_MODULE_ID index ) ;
7375 USART_MODULE_ID index ) ;
7401 USART_MODULE_ID index ) ;
7428 USART_MODULE_ID index ) ;
7454 USART_MODULE_ID index ) ;
7480 USART_MODULE_ID index ) ;
7505 USART_MODULE_ID index ) ;
7530 USART_MODULE_ID index ) ;
7555 USART_MODULE_ID index ) ;
7581 USART_MODULE_ID index ) ;
7606 USART_MODULE_ID index ) ;
7632 USART_MODULE_ID index ) ;
7658 USART_MODULE_ID index ) ;
7683 USART_MODULE_ID index ) ;
7709 USART_MODULE_ID index ) ;
7734 USART_MODULE_ID index ) ;
7759 USART_MODULE_ID index ) ;
7786 USART_MODULE_ID index ) ;
7811 USART_MODULE_ID index ) ;
7837 USART_MODULE_ID index ) ;
7902 #include "system/common/sys_common.h" 7903 #include "system/common/sys_module.h" 7915 #include "system/int/sys_int.h" 7987 #ifndef _SYS_DMA_DEFINITIONS_H 7988 #define _SYS_DMA_DEFINITIONS_H 7994 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7995 #include "system/common/sys_common.h" 7996 #include "system/common/sys_module.h" 8066 #ifndef _PLIB_DMA_PROCESSOR_H 8067 #define _PLIB_DMA_PROCESSOR_H 8068 #error "Can't find header" 8112 DMA_MODULE_ID index ,
8113 DMA_CHANNEL channel ) ;
8147 DMA_MODULE_ID index ,
8148 DMA_CHANNEL channel ,
8149 DMA_CHANNEL_COLLISION collisonType ) ;
8181 DMA_MODULE_ID index ,
8182 DMA_CHANNEL channel ) ;
8214 DMA_MODULE_ID index ,
8215 DMA_CHANNEL channel ) ;
8253 DMA_MODULE_ID index ,
8254 DMA_CHANNEL channel ,
8255 DMA_CHANNEL_PRIORITY channelPriority ) ;
8284 DMA_CHANNEL_PRIORITY
8286 DMA_MODULE_ID index ,
8287 DMA_CHANNEL channel ) ;
8315 DMA_MODULE_ID index ,
8316 DMA_CHANNEL_PRIORITY channelPriority ) ;
8341 DMA_CHANNEL_PRIORITY
8343 DMA_MODULE_ID index ) ;
8373 DMA_MODULE_ID index ,
8374 DMA_CHANNEL channel ) ;
8405 DMA_MODULE_ID index ,
8406 DMA_CHANNEL channel ) ;
8435 DMA_MODULE_ID index ,
8436 DMA_CHANNEL channel ) ;
8465 DMA_MODULE_ID index ,
8466 DMA_CHANNEL channel ) ;
8497 DMA_MODULE_ID index ,
8498 DMA_CHANNEL channel ) ;
8527 DMA_MODULE_ID index ,
8528 DMA_CHANNEL channel ) ;
8559 DMA_MODULE_ID index ,
8560 DMA_CHANNEL channel ) ;
8591 DMA_MODULE_ID index ,
8592 DMA_CHANNEL channel ) ;
8621 DMA_MODULE_ID index ,
8622 DMA_CHANNEL channel ) ;
8653 DMA_MODULE_ID index ,
8654 DMA_CHANNEL channel ) ;
8683 DMA_MODULE_ID index ,
8684 DMA_CHANNEL channel ) ;
8714 DMA_MODULE_ID index ,
8715 DMA_CHANNEL channel ) ;
8745 DMA_MODULE_ID index ,
8746 DMA_CHANNEL channel ) ;
8776 DMA_MODULE_ID index ,
8777 DMA_CHANNEL channel ) ;
8807 DMA_MODULE_ID index ,
8808 DMA_CHANNEL channel ) ;
8839 DMA_MODULE_ID index ,
8840 DMA_CHANNEL channel ) ;
8871 DMA_MODULE_ID index ,
8872 DMA_CHANNEL channel ,
8873 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8902 DMA_CHANNEL_TRANSFER_DIRECTION
8904 DMA_MODULE_ID index ,
8905 DMA_CHANNEL channel ) ;
8941 DMA_MODULE_ID index ,
8942 DMA_CHANNEL channel ,
8944 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8977 DMA_MODULE_ID index ,
8978 DMA_CHANNEL channel ,
8979 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9010 DMA_MODULE_ID index ,
9011 DMA_CHANNEL channel ,
9012 uint16_t peripheraladdress ) ;
9040 DMA_MODULE_ID index ,
9041 DMA_CHANNEL channel ) ;
9072 DMA_MODULE_ID index ,
9073 DMA_CHANNEL channel ,
9074 uint16_t transferCount ) ;
9102 DMA_MODULE_ID index ,
9103 DMA_CHANNEL channel ) ;
9136 DMA_MODULE_ID index ,
9137 DMA_CHANNEL channel ,
9138 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9166 DMA_SOURCE_ADDRESSING_MODE
9168 DMA_MODULE_ID index ,
9169 DMA_CHANNEL channel ) ;
9202 DMA_MODULE_ID index ,
9203 DMA_CHANNEL channel ,
9204 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9233 DMA_DESTINATION_ADDRESSING_MODE
9235 DMA_MODULE_ID index ,
9236 DMA_CHANNEL channel ) ;
9269 DMA_MODULE_ID index ,
9270 DMA_CHANNEL channel ,
9271 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9299 DMA_CHANNEL_ADDRESSING_MODE
9301 DMA_MODULE_ID index ,
9302 DMA_CHANNEL channel ) ;
9340 DMA_MODULE_ID index ,
9341 DMA_CHANNEL channel ,
9342 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9378 DMA_MODULE_ID index ,
9379 DMA_CHANNEL channel ,
9380 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9415 DMA_MODULE_ID index ,
9416 DMA_CHANNEL channel ,
9417 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9446 DMA_CHANNEL_INT_SOURCE
9448 DMA_MODULE_ID index ,
9449 DMA_CHANNEL channel ) ;
9484 DMA_MODULE_ID index ,
9485 DMA_CHANNEL channel ,
9486 DMA_TRIGGER_SOURCE IRQnum ) ;
9521 DMA_MODULE_ID index ,
9522 DMA_CHANNEL channel ,
9523 DMA_TRIGGER_SOURCE IRQ ) ;
9554 DMA_MODULE_ID index ,
9555 DMA_CHANNEL channel ,
9556 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9583 DMA_CHANNEL_DATA_SIZE
9585 DMA_MODULE_ID index ,
9586 DMA_CHANNEL channel ) ;
9620 DMA_MODULE_ID index ,
9621 DMA_CHANNEL channel ,
9622 DMA_TRANSFER_MODE channeltransferMode ) ;
9654 DMA_MODULE_ID index ,
9655 DMA_CHANNEL channel ) ;
9684 DMA_MODULE_ID index ,
9685 DMA_CHANNEL channel ) ;
9715 DMA_MODULE_ID index ,
9716 DMA_CHANNEL channel ) ;
9745 DMA_MODULE_ID index ,
9746 DMA_CHANNEL channel ) ;
9774 DMA_MODULE_ID index ,
9775 DMA_CHANNEL channel ) ;
9805 DMA_MODULE_ID index ,
9806 DMA_CHANNEL channel ) ;
9833 DMA_MODULE_ID index ,
9834 DMA_CHANNEL channel ) ;
9870 DMA_MODULE_ID index ,
9871 DMA_CHANNEL channel ) ;
9902 DMA_MODULE_ID index ,
9903 DMA_CHANNEL channel ) ;
9936 DMA_MODULE_ID index ) ;
9965 DMA_MODULE_ID index ) ;
9995 DMA_MODULE_ID index ) ;
10024 DMA_MODULE_ID index ) ;
10053 DMA_MODULE_ID index ) ;
10083 DMA_MODULE_ID index ) ;
10111 DMA_MODULE_ID index ) ;
10139 DMA_MODULE_ID index ) ;
10167 DMA_MODULE_ID index ) ;
10196 DMA_MODULE_ID index ) ;
10224 DMA_MODULE_ID index ) ;
10258 DMA_MODULE_ID index ) ;
10288 DMA_MODULE_ID index ) ;
10318 DMA_MODULE_ID index ) ;
10347 DMA_MODULE_ID index ) ;
10382 DMA_MODULE_ID index ,
10383 DMA_CHANNEL channel ) ;
10412 DMA_MODULE_ID index ) ;
10444 DMA_MODULE_ID index ,
10445 DMA_CRC_TYPE CRCType ) ;
10476 DMA_MODULE_ID index ) ;
10506 DMA_MODULE_ID index ) ;
10536 DMA_MODULE_ID index ) ;
10566 DMA_MODULE_ID index ) ;
10595 DMA_MODULE_ID index ) ;
10625 DMA_MODULE_ID index ) ;
10654 DMA_MODULE_ID index ) ;
10684 DMA_MODULE_ID index ,
10685 uint8_t polyLength ) ;
10714 DMA_MODULE_ID index ) ;
10743 DMA_MODULE_ID index ,
10744 DMA_CRC_BIT_ORDER bitOrder ) ;
10775 DMA_MODULE_ID index ) ;
10804 DMA_MODULE_ID index ) ;
10834 DMA_MODULE_ID index ,
10835 DMA_CRC_BYTE_ORDER byteOrder ) ;
10864 DMA_MODULE_ID index ) ;
10895 DMA_MODULE_ID index ) ;
10927 DMA_MODULE_ID index ,
10928 uint32_t DMACRCdata ) ;
10959 DMA_MODULE_ID index ) ;
10992 DMA_MODULE_ID index ,
10993 uint32_t DMACRCXOREnableMask ) ;
11031 DMA_MODULE_ID index ,
11032 DMA_CHANNEL dmaChannel ) ;
11069 DMA_MODULE_ID index ,
11070 DMA_CHANNEL dmaChannel ,
11071 uint32_t sourceStartAddress ) ;
11105 DMA_MODULE_ID index ,
11106 DMA_CHANNEL dmaChannel ) ;
11144 DMA_MODULE_ID index ,
11145 DMA_CHANNEL dmaChannel ,
11146 uint32_t destinationStartAddress ) ;
11186 DMA_MODULE_ID index ,
11187 DMA_CHANNEL dmaChannel ) ;
11226 DMA_MODULE_ID index ,
11227 DMA_CHANNEL dmaChannel ,
11228 uint16_t sourceSize ) ;
11263 DMA_MODULE_ID index ,
11264 DMA_CHANNEL dmaChannel ) ;
11301 DMA_MODULE_ID index ,
11302 DMA_CHANNEL dmaChannel ,
11303 uint16_t destinationSize ) ;
11337 DMA_MODULE_ID index ,
11338 DMA_CHANNEL dmaChannel ) ;
11373 DMA_MODULE_ID index ,
11374 DMA_CHANNEL dmaChannel ) ;
11409 DMA_MODULE_ID index ,
11410 DMA_CHANNEL dmaChannel ) ;
11447 DMA_MODULE_ID index ,
11448 DMA_CHANNEL dmaChannel ,
11449 uint16_t CellSize ) ;
11483 DMA_MODULE_ID index ,
11484 DMA_CHANNEL dmaChannel ) ;
11521 DMA_MODULE_ID index ,
11522 DMA_CHANNEL dmaChannel ) ;
11561 DMA_MODULE_ID index ,
11562 DMA_CHANNEL dmaChannel ,
11563 uint16_t patternData ) ;
11607 DMA_MODULE_ID index ,
11608 DMA_CHANNEL dmaChannel ,
11609 DMA_INT_TYPE dmaINTSource ) ;
11644 DMA_MODULE_ID index ,
11645 DMA_CHANNEL dmaChannel ,
11646 DMA_INT_TYPE dmaINTSource ) ;
11682 DMA_MODULE_ID index ,
11683 DMA_CHANNEL dmaChannel ,
11684 DMA_INT_TYPE dmaINTSource ) ;
11718 DMA_MODULE_ID index ,
11719 DMA_CHANNEL dmaChannel ,
11720 DMA_INT_TYPE dmaINTSource ) ;
11754 DMA_MODULE_ID index ,
11755 DMA_CHANNEL dmaChannel ,
11756 DMA_INT_TYPE dmaINTSource ) ;
11794 DMA_MODULE_ID index ,
11795 DMA_CHANNEL dmaChannel ,
11796 DMA_INT_TYPE dmaINTSource ) ;
11829 DMA_MODULE_ID index ,
11830 DMA_CHANNEL dmaChannel ,
11831 DMA_PATTERN_LENGTH patternLen ) ;
11864 DMA_MODULE_ID index ,
11865 DMA_CHANNEL dmaChannel ) ;
11895 DMA_MODULE_ID index ,
11896 DMA_CHANNEL channel ) ;
11929 DMA_MODULE_ID index ,
11930 DMA_CHANNEL channel ) ;
11960 DMA_MODULE_ID index ,
11961 DMA_CHANNEL channel ) ;
11993 DMA_MODULE_ID index ,
11994 DMA_CHANNEL channel ,
11995 uint8_t pattern ) ;
12026 DMA_MODULE_ID index ,
12027 DMA_CHANNEL channel ) ;
12059 DMA_MODULE_ID index ) ;
12084 DMA_MODULE_ID index ) ;
12108 DMA_MODULE_ID index ) ;
12133 DMA_MODULE_ID index ) ;
12156 DMA_MODULE_ID index ) ;
12180 DMA_MODULE_ID index ) ;
12203 DMA_MODULE_ID index ) ;
12227 DMA_MODULE_ID index ) ;
12251 DMA_MODULE_ID index ) ;
12276 DMA_MODULE_ID index ) ;
12300 DMA_MODULE_ID index ) ;
12324 DMA_MODULE_ID index ) ;
12347 DMA_MODULE_ID index ) ;
12371 DMA_MODULE_ID index ) ;
12395 DMA_MODULE_ID index ) ;
12419 DMA_MODULE_ID index ) ;
12443 DMA_MODULE_ID index ) ;
12467 DMA_MODULE_ID index ) ;
12490 DMA_MODULE_ID index ) ;
12515 DMA_MODULE_ID index ) ;
12540 DMA_MODULE_ID index ) ;
12564 DMA_MODULE_ID index ) ;
12589 DMA_MODULE_ID index ) ;
12613 DMA_MODULE_ID index ) ;
12637 DMA_MODULE_ID index ) ;
12663 DMA_MODULE_ID index ) ;
12688 DMA_MODULE_ID index ) ;
12712 DMA_MODULE_ID index ) ;
12737 DMA_MODULE_ID index ) ;
12760 DMA_MODULE_ID index ) ;
12783 DMA_MODULE_ID index ) ;
12806 DMA_MODULE_ID index ) ;
12829 DMA_MODULE_ID index ) ;
12854 DMA_MODULE_ID index ) ;
12879 DMA_MODULE_ID index ) ;
12903 DMA_MODULE_ID index ) ;
12928 DMA_MODULE_ID index ) ;
12952 DMA_MODULE_ID index ) ;
12976 DMA_MODULE_ID index ) ;
12999 DMA_MODULE_ID index ) ;
13022 DMA_MODULE_ID index ) ;
13046 DMA_MODULE_ID index ) ;
13070 DMA_MODULE_ID index ) ;
13094 DMA_MODULE_ID index ) ;
13121 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13134 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13147 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13177 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13351 DMA_CRC_TYPE type ;
13357 uint8_t polyLength ;
13360 DMA_CRC_BIT_ORDER bitOrder ;
13363 DMA_CRC_BYTE_ORDER byteOrder ;
13373 uint32_t xorBitMask ;
13498 SYS_MODULE_OBJ
object ,
13499 DMA_CHANNEL activeChannel ) ;
13502 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13547 uintptr_t contextHandle ) ;
13593 const SYS_MODULE_INIT *
const init ) ;
13644 DMA_CHANNEL channel ) ;
13730 DMA_TRIGGER_SOURCE eventSrc ) ;
13808 DMA_PATTERN_LENGTH length ,
13810 uint8_t ignorePattern ) ;
14063 const void * srcAddr ,
14065 const void * destAddr ,
14067 size_t cellSize ) ;
14164 const void * srcAddr ,
14166 const void * destAddr ,
14168 size_t cellSize ) ;
14364 const uintptr_t contextHandle ) ;
14660 DMA_TRIGGER_SOURCE eventSrc ) ;
14839 SYS_MODULE_OBJ
object ,
14840 DMA_CHANNEL activeChannel ) ;
14850 SYS_MODULE_OBJ
object ) ;
14860 SYS_MODULE_OBJ
object ,
14861 DMA_CHANNEL activeChannel ) ;
14888 #define DRV_USART_INDEX_0 0 14889 #define DRV_USART_INDEX_1 1 14890 #define DRV_USART_INDEX_2 2 14891 #define DRV_USART_INDEX_3 3 14892 #define DRV_USART_INDEX_4 4 14893 #define DRV_USART_INDEX_5 5 14907 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14918 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14929 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14963 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15114 uintptr_t context ) ;
15162 USART_HANDSHAKE_MODE_FLOW_CONTROL
15166 USART_HANDSHAKE_MODE_SIMPLEX
15328 } AddressedModeInit ;
15353 = USART_ERROR_PARITY
15358 = USART_ERROR_FRAMING
15363 = USART_ERROR_RECEIVER_OVERRUN
15445 SYS_MODULE_INIT moduleInit ;
15449 USART_MODULE_ID usartID ;
15467 uint32_t brgClock ;
15483 USART_OPERATION_MODE linesEnable ;
15487 INT_SOURCE interruptTransmit ;
15491 INT_SOURCE interruptReceive ;
15495 INT_SOURCE interruptError ;
15500 unsigned int queueSizeReceive ;
15505 unsigned int queueSizeTransmit ;
15509 DMA_CHANNEL dmaChannelTransmit ;
15513 DMA_CHANNEL dmaChannelReceive ;
15517 INT_SOURCE dmaInterruptTransmit ;
15521 INT_SOURCE dmaInterruptReceive ;
15605 const SYS_MODULE_INDEX index ,
15606 const SYS_MODULE_INIT *
const init ) ;
15644 SYS_MODULE_OBJ
object ) ;
15682 SYS_MODULE_OBJ
object ) ;
15723 SYS_MODULE_OBJ
object ) ;
15764 SYS_MODULE_OBJ
object ) ;
15805 SYS_MODULE_OBJ
object ) ;
15884 const SYS_MODULE_INDEX index ,
16068 const size_t size ) ;
16261 const size_t size ) ;
16349 const uintptr_t context ) ;
16616 const size_t numbytes ) ;
16684 const size_t numbytes ) ;
16821 const uint8_t byte ) ;
17039 const SYS_MODULE_INDEX index ,
17092 const SYS_MODULE_INDEX index ,
17141 const SYS_MODULE_INDEX index ,
17356 #ifndef _DRV_USART_FEATURE_MAPPING_H 17357 #define _DRV_USART_FEATURE_MAPPING_H 17366 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17367 #define _DRV_USART_InterruptSourceEnable( source ) 17368 #define _DRV_USART_InterruptSourceDisable( source ) false 17369 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17370 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17371 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17372 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17373 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17376 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17385 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17386 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17387 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17388 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17389 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17402 #include "system/clk/sys_clk.h" 17403 #include "system/int/sys_int.h" 17441 #ifndef _SYS_DEBUG_H 17442 #define _SYS_DEBUG_H 17443 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17446 #define SYS_DEBUG_BUFFER_DMA_READY 17496 #define SYS_DEBUG_INDEX_0 0 17512 SYS_MODULE_INIT moduleInit ;
17516 SYS_MODULE_INDEX consoleIndex ;
17564 const SYS_MODULE_INDEX index ,
17565 const SYS_MODULE_INIT *
const init ) ;
17605 SYS_MODULE_OBJ
object ,
17606 const SYS_MODULE_INIT *
const init ) ;
17636 SYS_MODULE_OBJ
object ) ;
17669 SYS_MODULE_OBJ
object ) ;
17713 SYS_MODULE_OBJ
object ) ;
17756 const char * message ) ;
17806 const char * format ,
17896 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17940 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17983 #define SYS_MESSAGE( message ) 18016 #define SYS_DEBUG_MESSAGE( level , message ) 18063 #define SYS_PRINT( fmt ,... ) 18111 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18136 #define SYS_DEBUG_BreakPoint( ) 18145 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18146 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18147 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18164 #define _DRV_USART_RX_DEPTH 9 18230 const SYS_MODULE_INDEX index ,
18255 const uint8_t byte ) ;
18326 #ifndef _SYS_PORTS_H 18327 #define _SYS_PORTS_H 18366 #ifndef _SYS_PORTS_DEFINITIONS_H 18367 #define _SYS_PORTS_DEFINITIONS_H 18373 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18374 #include "system/common/sys_common.h" 18375 #include "system/common/sys_module.h" 18412 #ifndef _PLIB_PORTS_H 18413 #define _PLIB_PORTS_H 18414 #include <stdint.h> 18415 #include <stddef.h> 18480 #ifndef _PLIB_PORTS_PROCESSOR_H 18481 #define _PLIB_PORTS_PROCESSOR_H 18482 #error "Can't find header" 18532 PORTS_MODULE_ID index ,
18533 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18534 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18577 PORTS_MODULE_ID index ,
18578 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18579 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18614 PORTS_MODULE_ID index ,
18615 PORTS_ANALOG_PIN pin ,
18616 PORTS_PIN_MODE mode ) ;
18656 PORTS_MODULE_ID index ,
18657 PORTS_CHANNEL channel ,
18658 PORTS_BIT_POS bitPos ,
18659 PORTS_PIN_MODE mode ) ;
18694 PORTS_MODULE_ID index ,
18695 PORTS_CHANNEL channel ,
18696 PORTS_BIT_POS bitPos ) ;
18730 PORTS_MODULE_ID index ,
18731 PORTS_CHANNEL channel ,
18732 PORTS_BIT_POS bitPos ) ;
18769 PORTS_MODULE_ID index ,
18770 PORTS_CHANNEL channel ,
18771 PORTS_BIT_POS bitPos ) ;
18812 PORTS_MODULE_ID index ,
18813 PORTS_CHANNEL channel ,
18814 PORTS_BIT_POS bitPos ) ;
18853 PORTS_MODULE_ID index ,
18854 PORTS_CHANNEL channel ,
18855 PORTS_BIT_POS bitPos ) ;
18893 PORTS_MODULE_ID index ,
18894 PORTS_CHANNEL channel ,
18895 PORTS_BIT_POS bitPos ) ;
18930 PORTS_MODULE_ID index ,
18931 PORTS_CHANNEL channel ) ;
18966 PORTS_MODULE_ID index ,
18967 PORTS_CHANNEL channel ) ;
19004 PORTS_MODULE_ID index ,
19005 PORTS_CHANNEL channel ) ;
19042 PORTS_MODULE_ID index ,
19043 PORTS_CHANNEL channel ) ;
19080 PORTS_MODULE_ID index ,
19081 PORTS_CHANNEL channel ,
19082 PORTS_BIT_POS bitPos ) ;
19119 PORTS_MODULE_ID index ,
19120 PORTS_CHANNEL channel ,
19121 PORTS_BIT_POS bitPos ) ;
19159 PORTS_MODULE_ID index ,
19160 PORTS_CHANNEL channel ,
19161 PORTS_BIT_POS bitPos ) ;
19198 PORTS_MODULE_ID index ,
19199 PORTS_CHANNEL channel ,
19200 PORTS_BIT_POS bitPos ,
19235 PORTS_MODULE_ID index ,
19236 PORTS_CHANNEL channel ,
19237 PORTS_BIT_POS bitPos ) ;
19271 PORTS_MODULE_ID index ,
19272 PORTS_CHANNEL channel ,
19273 PORTS_BIT_POS bitPos ) ;
19307 PORTS_MODULE_ID index ,
19308 PORTS_CHANNEL channel ,
19309 PORTS_BIT_POS bitPos ) ;
19344 PORTS_MODULE_ID index ,
19345 PORTS_CHANNEL channel ,
19346 PORTS_BIT_POS bitPos ) ;
19381 PORTS_MODULE_ID index ,
19382 PORTS_CHANNEL channel ,
19383 PORTS_BIT_POS bitPos ) ;
19417 PORTS_MODULE_ID index ,
19418 PORTS_CHANNEL channel ,
19419 PORTS_BIT_POS bitPos ) ;
19453 PORTS_MODULE_ID index ,
19454 PORTS_CHANNEL channel ,
19455 PORTS_BIT_POS bitPos ) ;
19493 PORTS_MODULE_ID index ,
19494 PORTS_CHANNEL channel ) ;
19528 PORTS_MODULE_ID index ,
19529 PORTS_CHANNEL channel ) ;
19563 PORTS_MODULE_ID index ,
19564 PORTS_CHANNEL channel ,
19607 PORTS_MODULE_ID index ,
19608 PORTS_CHANNEL channel ,
19644 PORTS_MODULE_ID index ,
19645 PORTS_CHANNEL channel ,
19680 PORTS_MODULE_ID index ,
19681 PORTS_CHANNEL channel ,
19717 PORTS_MODULE_ID index ,
19718 PORTS_CHANNEL channel ,
19753 PORTS_MODULE_ID index ,
19754 PORTS_CHANNEL channel ,
19787 PORTS_MODULE_ID index ,
19788 PORTS_CHANNEL channel ) ;
19822 PORTS_MODULE_ID index ,
19823 PORTS_CHANNEL channel ,
19859 PORTS_MODULE_ID index ,
19860 PORTS_CHANNEL channel ,
19906 PORTS_MODULE_ID index ,
19907 PORTS_CHANNEL channel ,
19909 PORTS_PIN_MODE mode ) ;
19951 PORTS_MODULE_ID index ,
19952 PORTS_CHANNEL channel ,
19995 PORTS_MODULE_ID index ,
19996 PORTS_CHANNEL channel ,
20036 PORTS_MODULE_ID index ,
20037 PORTS_CHANNEL channel ,
20077 PORTS_MODULE_ID index ,
20078 PORTS_CHANNEL channel ,
20122 PORTS_MODULE_ID index ,
20123 PORTS_CHANNEL channel ,
20167 PORTS_MODULE_ID index ,
20168 PORTS_CHANNEL channel ,
20214 PORTS_MODULE_ID index ,
20215 PORTS_AN_PIN anPins ,
20216 PORTS_PIN_MODE mode ) ;
20259 PORTS_MODULE_ID index ,
20260 PORTS_CN_PIN cnPins ) ;
20304 PORTS_MODULE_ID index ,
20305 PORTS_CN_PIN cnPins ) ;
20348 PORTS_MODULE_ID index ,
20349 PORTS_CN_PIN cnPins ) ;
20392 PORTS_MODULE_ID index ,
20393 PORTS_CN_PIN cnPins ) ;
20427 PORTS_MODULE_ID index ) ;
20460 PORTS_MODULE_ID index ) ;
20496 PORTS_MODULE_ID index ,
20497 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20533 PORTS_MODULE_ID index ,
20534 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20571 PORTS_MODULE_ID index ) ;
20605 PORTS_MODULE_ID index ) ;
20641 PORTS_MODULE_ID index ,
20642 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20678 PORTS_MODULE_ID index ,
20679 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20724 PORTS_MODULE_ID index ,
20725 PORTS_CHANNEL channel ,
20727 PORTS_PIN_SLEW_RATE slewRate ) ;
20764 PORTS_PIN_SLEW_RATE
20766 PORTS_MODULE_ID index ,
20767 PORTS_CHANNEL channel ,
20768 PORTS_BIT_POS bitPos ) ;
20807 PORTS_MODULE_ID index ,
20808 PORTS_CHANNEL channel ,
20809 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20842 PORTS_CHANGE_NOTICE_METHOD
20844 PORTS_MODULE_ID index ,
20845 PORTS_CHANNEL channel ) ;
20893 PORTS_MODULE_ID index ,
20894 PORTS_CHANNEL channel ,
20944 PORTS_MODULE_ID index ,
20945 PORTS_CHANNEL channel ,
20993 PORTS_MODULE_ID index ,
20994 PORTS_CHANNEL channel ,
20995 PORTS_BIT_POS bitPos ,
20996 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21039 PORTS_MODULE_ID index ,
21040 PORTS_CHANNEL channel ,
21041 PORTS_BIT_POS bitPos ) ;
21072 PORTS_MODULE_ID index ) ;
21096 PORTS_MODULE_ID index ) ;
21120 PORTS_MODULE_ID index ) ;
21144 PORTS_MODULE_ID index ) ;
21169 PORTS_MODULE_ID index ) ;
21194 PORTS_MODULE_ID index ) ;
21225 PORTS_MODULE_ID index ) ;
21253 PORTS_MODULE_ID index ) ;
21280 PORTS_MODULE_ID index ) ;
21305 PORTS_MODULE_ID index ) ;
21332 PORTS_MODULE_ID index ) ;
21357 PORTS_MODULE_ID index ) ;
21384 PORTS_MODULE_ID index ) ;
21409 PORTS_MODULE_ID index ) ;
21437 PORTS_MODULE_ID index ) ;
21465 PORTS_MODULE_ID index ) ;
21493 PORTS_MODULE_ID index ) ;
21519 PORTS_MODULE_ID index ) ;
21545 PORTS_MODULE_ID index ) ;
21571 PORTS_MODULE_ID index ) ;
21596 PORTS_MODULE_ID index ) ;
21622 PORTS_MODULE_ID index ) ;
21649 PORTS_MODULE_ID index ) ;
21674 PORTS_MODULE_ID index ) ;
21709 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21710 #define _PLIB_PORTS_COMPATIBILITY_H 21711 #include <stdint.h> 21712 #include <stddef.h> 21747 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21764 #include "system/int/sys_int.h" 21898 PORTS_MODULE_ID index ,
21899 PORTS_CHANNEL channel ) ;
21931 PORTS_MODULE_ID index ,
21932 PORTS_CHANNEL channel ,
21962 PORTS_MODULE_ID index ,
21963 PORTS_CHANNEL channel ) ;
22001 PORTS_MODULE_ID index ,
22002 PORTS_CHANNEL channel ,
22036 PORTS_MODULE_ID index ,
22037 PORTS_CHANNEL channel ,
22074 PORTS_MODULE_ID index ,
22076 PORTS_CHANNEL channel ,
22106 PORTS_MODULE_ID index ,
22107 PORTS_CHANNEL channel ) ;
22138 PORTS_MODULE_ID index ,
22139 PORTS_CHANNEL channel ,
22171 PORTS_MODULE_ID index ,
22172 PORTS_CHANNEL channel ,
22204 PORTS_MODULE_ID index ,
22205 PORTS_CHANNEL channel ,
22239 PORTS_MODULE_ID index ,
22240 PORTS_CHANNEL channel ) ;
22280 PORTS_MODULE_ID index ,
22281 PORTS_REMAP_INPUT_FUNCTION
function ,
22282 PORTS_REMAP_INPUT_PIN remapPin ) ;
22317 PORTS_MODULE_ID index ,
22318 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22319 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22352 PORTS_MODULE_ID index ) ;
22380 PORTS_MODULE_ID index ) ;
22414 PORTS_MODULE_ID index ,
22415 PORTS_CHANGE_NOTICE_PIN pinNum ,
22447 PORTS_MODULE_ID index ,
22448 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22477 PORTS_MODULE_ID index ) ;
22506 PORTS_MODULE_ID index ) ;
22537 PORTS_MODULE_ID index ,
22538 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22569 PORTS_MODULE_ID index ,
22570 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22609 PORTS_MODULE_ID index ,
22610 PORTS_ANALOG_PIN pin ,
22611 PORTS_PIN_MODE mode ) ;
22648 PORTS_MODULE_ID index ,
22649 PORTS_CHANNEL channel ,
22650 PORTS_BIT_POS bitPos ,
22685 PORTS_MODULE_ID index ,
22686 PORTS_CHANNEL channel ,
22687 PORTS_BIT_POS bitPos ) ;
22720 PORTS_MODULE_ID index ,
22721 PORTS_CHANNEL channel ,
22722 PORTS_BIT_POS bitPos ) ;
22755 PORTS_MODULE_ID index ,
22756 PORTS_CHANNEL channel ,
22757 PORTS_BIT_POS bitPos ) ;
22790 PORTS_MODULE_ID index ,
22791 PORTS_CHANNEL channel ,
22792 PORTS_BIT_POS bitPos ) ;
22825 PORTS_MODULE_ID index ,
22826 PORTS_CHANNEL channel ,
22827 PORTS_BIT_POS bitPos ) ;
22864 PORTS_MODULE_ID index ,
22866 PORTS_CHANNEL channel ,
22867 PORTS_BIT_POS bitPos ) ;
22900 PORTS_MODULE_ID index ,
22901 PORTS_CHANNEL channel ,
22902 PORTS_BIT_POS bitPos ) ;
22935 PORTS_MODULE_ID index ,
22936 PORTS_CHANNEL channel ,
22937 PORTS_BIT_POS bitPos ) ;
22970 PORTS_MODULE_ID index ,
22971 PORTS_CHANNEL channel ,
22972 PORTS_BIT_POS bitPos ) ;
23005 PORTS_MODULE_ID index ,
23006 PORTS_CHANNEL channel ,
23007 PORTS_BIT_POS bitPos ) ;
23040 PORTS_MODULE_ID index ,
23041 PORTS_CHANNEL channel ,
23042 PORTS_BIT_POS bitPos ) ;
23075 PORTS_MODULE_ID index ,
23076 PORTS_CHANNEL channel ,
23077 PORTS_BIT_POS bitPos ) ;
23110 PORTS_MODULE_ID index ,
23111 PORTS_CHANNEL channel ,
23112 PORTS_BIT_POS bitPos ,
23195 #ifndef _DRV_SPI_DEFINITIONS_H 23196 #define _DRV_SPI_DEFINITIONS_H 23202 #include <stdint.h> 23203 #include <stdbool.h> 23204 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23205 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23241 #ifndef _PLIB_SPI_H 23242 #define _PLIB_SPI_H 23276 #ifndef _PLIB_SPI_PROCESSOR_H 23277 #define _PLIB_SPI_PROCESSOR_H 23278 #error "Can't find header" 23323 SPI_MODULE_ID index ) ;
23353 SPI_MODULE_ID index ) ;
23385 SPI_MODULE_ID index ) ;
23417 SPI_MODULE_ID index ) ;
23451 SPI_MODULE_ID index ) ;
23481 SPI_MODULE_ID index ) ;
23518 SPI_MODULE_ID index ) ;
23557 SPI_MODULE_ID index ) ;
23587 SPI_MODULE_ID index ,
23618 SPI_MODULE_ID index ,
23652 SPI_MODULE_ID index ,
23653 SPI_COMMUNICATION_WIDTH width ) ;
23688 SPI_MODULE_ID index ,
23689 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23721 SPI_MODULE_ID index ,
23722 SPI_INPUT_SAMPLING_PHASE phase ) ;
23754 SPI_MODULE_ID index ,
23755 SPI_OUTPUT_DATA_PHASE phase ) ;
23786 SPI_MODULE_ID index ,
23787 SPI_CLOCK_POLARITY polarity ) ;
23817 SPI_MODULE_ID index ) ;
23847 SPI_MODULE_ID index ) ;
23885 SPI_MODULE_ID index ,
23886 uint32_t clockFrequency ,
23887 uint32_t baudRate ) ;
23918 SPI_MODULE_ID index ) ;
23950 SPI_MODULE_ID index ) ;
23983 SPI_MODULE_ID index ) ;
24016 SPI_MODULE_ID index ) ;
24048 SPI_MODULE_ID index ) ;
24078 SPI_MODULE_ID index ) ;
24109 SPI_MODULE_ID index ) ;
24140 SPI_MODULE_ID index ) ;
24171 SPI_MODULE_ID index ) ;
24203 SPI_MODULE_ID index ,
24204 SPI_FIFO_TYPE type ) ;
24236 SPI_MODULE_ID index ) ;
24268 SPI_MODULE_ID index ) ;
24302 SPI_MODULE_ID index ,
24303 SPI_FIFO_INTERRUPT mode ) ;
24333 SPI_MODULE_ID index ) ;
24363 SPI_MODULE_ID index ) ;
24395 SPI_MODULE_ID index ,
24396 SPI_FRAME_PULSE_DIRECTION direction ) ;
24429 SPI_MODULE_ID index ,
24430 SPI_FRAME_PULSE_POLARITY polarity ) ;
24463 SPI_MODULE_ID index ,
24464 SPI_FRAME_PULSE_EDGE edge ) ;
24497 SPI_MODULE_ID index ,
24498 SPI_FRAME_PULSE_WIDTH width ) ;
24532 SPI_MODULE_ID index ,
24533 SPI_FRAME_SYNC_PULSE pulse ) ;
24565 SPI_MODULE_ID index ) ;
24595 SPI_MODULE_ID index ) ;
24627 SPI_MODULE_ID index ) ;
24657 SPI_MODULE_ID index ) ;
24687 SPI_MODULE_ID index ) ;
24717 SPI_MODULE_ID index ) ;
24748 SPI_MODULE_ID index ,
24780 SPI_MODULE_ID index ,
24812 SPI_MODULE_ID index ,
24835 SPI_MODULE_ID index ) ;
24866 SPI_MODULE_ID index ,
24867 SPI_BAUD_RATE_CLOCK type ) ;
24899 SPI_MODULE_ID index ,
24900 SPI_ERROR_INTERRUPT error ) ;
24932 SPI_MODULE_ID index ,
24933 SPI_ERROR_INTERRUPT error ) ;
24964 SPI_MODULE_ID index ,
24965 SPI_AUDIO_ERROR error ) ;
24996 SPI_MODULE_ID index ,
24997 SPI_AUDIO_ERROR error ) ;
25027 SPI_MODULE_ID index ) ;
25057 SPI_MODULE_ID index ) ;
25089 SPI_MODULE_ID index ,
25090 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25122 SPI_MODULE_ID index ,
25123 SPI_AUDIO_PROTOCOL mode ) ;
25156 SPI_MODULE_ID index ) ;
25182 SPI_MODULE_ID index ) ;
25208 SPI_MODULE_ID index ) ;
25233 SPI_MODULE_ID index ) ;
25258 SPI_MODULE_ID index ) ;
25283 SPI_MODULE_ID index ) ;
25309 SPI_MODULE_ID index ) ;
25334 SPI_MODULE_ID index ) ;
25359 SPI_MODULE_ID index ) ;
25384 SPI_MODULE_ID index ) ;
25409 SPI_MODULE_ID index ) ;
25434 SPI_MODULE_ID index ) ;
25460 SPI_MODULE_ID index ) ;
25485 SPI_MODULE_ID index ) ;
25510 SPI_MODULE_ID index ) ;
25535 SPI_MODULE_ID index ) ;
25561 SPI_MODULE_ID index ) ;
25587 SPI_MODULE_ID index ) ;
25613 SPI_MODULE_ID index ) ;
25637 SPI_MODULE_ID index ) ;
25662 SPI_MODULE_ID index ) ;
25687 SPI_MODULE_ID index ) ;
25712 SPI_MODULE_ID index ) ;
25738 SPI_MODULE_ID index ) ;
25763 SPI_MODULE_ID index ) ;
25788 SPI_MODULE_ID index ) ;
25813 SPI_MODULE_ID index ) ;
25838 SPI_MODULE_ID index ) ;
25863 SPI_MODULE_ID index ) ;
25889 SPI_MODULE_ID index ) ;
25916 SPI_MODULE_ID index ) ;
25941 SPI_MODULE_ID index ) ;
25967 SPI_MODULE_ID index ) ;
25993 SPI_MODULE_ID index ) ;
26019 SPI_MODULE_ID index ) ;
26044 SPI_MODULE_ID index ) ;
26069 SPI_MODULE_ID index ) ;
26095 SPI_MODULE_ID index ) ;
26121 SPI_MODULE_ID index ) ;
26133 #include "system/common/sys_common.h" 26134 #include "system/common/sys_module.h" 26135 #include "system/int/sys_int.h" 26136 #include "system/clk/sys_clk.h" 26137 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26175 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26187 #define DRV_SPI_INDEX_0 0 26188 #define DRV_SPI_INDEX_1 1 26189 #define DRV_SPI_INDEX_2 2 26190 #define DRV_SPI_INDEX_3 3 26191 #define DRV_SPI_INDEX_4 4 26192 #define DRV_SPI_INDEX_5 5 26204 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26453 SPI_MODULE_ID
spiId ;
26486 CLK_BUSES_PERIPHERAL
spiClk ;
26646 const SYS_MODULE_INDEX index ,
26647 const SYS_MODULE_INIT *
const init ) ;
26689 SYS_MODULE_OBJ
object ) ;
26738 SYS_MODULE_OBJ
object ) ;
26779 SYS_MODULE_OBJ
object ) ;
26844 const SYS_MODULE_INDEX drvIndex ,
27439 #include "driver/usb/usbhs/drv_usbhs.h" 27440 #include "usb/usb_device.h" 27468 #include <stdint.h> 27488 uint8_t RevNumber ;
27575 SYS_MODULE_OBJ sysTmr ;
27576 SYS_MODULE_OBJ drvTmr0 ;
27577 SYS_MODULE_OBJ drvTmr1 ;
27578 SYS_MODULE_OBJ drvTmr2 ;
27579 SYS_MODULE_OBJ drvTmr3 ;
27580 SYS_MODULE_OBJ drvTmr4 ;
27581 SYS_MODULE_OBJ drvUsart0 ;
27582 SYS_MODULE_OBJ drvPMP0 ;
27584 SYS_MODULE_OBJ spiObjectIdx0 ;
27586 SYS_MODULE_OBJ spiObjectIdx1 ;
27588 SYS_MODULE_OBJ spiObjectIdx2 ;
27589 SYS_MODULE_OBJ drvUSBObject ;
27590 SYS_MODULE_OBJ usbDevObject0 ;
27625 #define ManHalfUpper 11800U 27626 #define ManHalfLower 2000U 27627 #define ManFullUpper 20000U 27628 #define ManFullLower 11801U 27629 #define NoManBits 32U 27630 #define HalfBit 0x12U 27631 #define FullBit 0x10U 27632 #define SizeOfBiasLUT 48U 27712 uint16_t preamble [ 5 ] ;
27713 uint16_t time [ 96 ] ;
27714 uint8_t level [ 96 ] ;
27715 uint8_t ans [ 32U + 2 ] ;
27716 uint8_t msg [ 4 ] ;
27717 uint8_t cnt_preamble ;
27718 uint8_t trynumber ;
27719 bool process_complete_flag ;
27720 bool spi_write_complete_flag ;
27721 bool spi_sent_flag ;
27722 uint8_t timer_count ;
27723 uint8_t timer_complete ;
27727 bool manual_bias_flag ;
27750 uint16_t adj [ 1 ] ;
27751 uint16_t dac_a_setting ;
27752 uint16_t dac_b_setting ;
28142 #include <stdint.h> 28181 uint8_t thebits ) ;
28210 const uint8_t Bytes [] ) ;
28241 const uint8_t Bytes [] ) ;
28324 #include "../system_config.h" 28325 #include "../system_definitions.h" 28370 uint8_t null_count ;
28371 bool send_message_complete_flag ;
28378 uint8_t table_count ;
28390 uint8_t byte [ 4 ] ;
28410 uint8_t identifier ;
28412 uint8_t msg_length ;
28413 uint8_t xmit_ready_flag ;
28498 static const uint8_t
28500 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
28501 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
28502 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
28503 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
28504 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
28505 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U
28506 , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U ,
28507 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU
28508 , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU ,
28509 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U
28510 , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
28512 static const uint8_t
28514 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
28515 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
28516 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
28517 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
28518 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
28519 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
28555 uint8_t Identifier ,
28557 uint8_t Msg_Length ) ;
28771 #include "../system_definitions.h" 28800 int8_t v_adj [ 1 ] ;
28802 uint16_t voltage_limit ;
28804 uint16_t max_current ;
28805 uint8_t current_limit ;
28806 uint8_t upper_current_limit ;
28807 uint8_t over_current_count ;
28810 bool new_voltage_flag ;
28811 bool new_current_flag ;
28812 bool spi_write_complete_flag ;
28813 bool spi_sent_flag ;
28814 uint8_t avg_count ;
28815 uint8_t avg_count_max ;
28816 uint16_t current_array [ 5 ] ;
28817 uint16_t avg_current ;
28818 uint8_t overvoltage_count ;
29022 #include <stdint.h> 29023 #include <stdbool.h> 29024 #include "../system_config.h" 29025 #include "../system_definitions.h" 29064 bool timer1_100uS_tick ;
29065 bool timer1_1mS_tick ;
29066 bool timer1_10mS_tick ;
29067 bool timer1_100mS_tick ;
29068 bool timer1_1000mS_tick ;
29069 uint8_t timer1_100uS_count ;
29070 uint8_t timer1_1mS_count ;
29071 uint8_t timer1_10mS_count ;
29072 uint8_t timer1_100mS_count ;
29073 uint8_t timer1_1000mS_count ;
29137 #include <stdbool.h> 29138 #include <stdint.h> 29179 uint8_t command [ 7 ] ;
29180 bool process_complete_flag ;
29181 bool b_command_complete_flag ;
29182 bool sw_status_bit_check ;
29419 #include <stdbool.h> 29420 #include <stdint.h> 29452 uint8_t bitposn ) ;
29478 uint8_t bitposn ) ;
29549 #include <stdbool.h> 29550 #include <stdint.h> 29551 #include <stdlib.h> 29599 static const uint8_t
29601 0x18U , 0x1DU , 0x22U , 0x26U , 0x2BU , 0x30U , 0x35U , 0x39U , 0x3EU , 0x43U , 0x48U , 0x4CU , 0x51U , 0x56U , 0x5BU , 0x5FU , 0x64U , 0x69U , 0x6EU , 0x72U , 0x77U , 0x7CU , 0x81U , 0x85U , 0x8AU , 0x8FU , 0x94U ,
29602 0x98U , 0x9DU , 0xA2U , 0xA7U , 0xABU , 0xB0U , 0xB5U , 0xBAU , 0xBEU , 0xC3U , 0xC8U , 0xCDU , 0xD1U , 0xD6U , 0xDBU , 0xE0U , 0xE4U , 0xE9U , 0xEEU , 0xF3U , 0xFFU } ;
29615 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
29647 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 0)));
29831 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 3)));
29861 timer_value >= 2000U
29866 ( timer_value <= 11800U )
29902 timer_value >= 2000U
29907 ( timer_value <= 11800U )
29929 timer_value >= 11801U
29934 ( timer_value <= 20000U )
29981 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 28)));
30056 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 11)));
30109 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 15)));
30119 cnt2 < ( 32U + 2U )
30124 int zzqqzs = ((int)(
bitmapstruct.element4 |= (1 << 16)));
30134 MAN.
ans[ cnt2 ] = 0x01U ;
30142 MAN.
ans[ cnt2 ] = 0x00U ;
30147 MAN.
time[ cnt + 1U ] == 0x12U
30185 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 26)));
30203 int QZZZ = ((int)(
bitmapstruct.element4 |= (1 << 29)));
30240 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 3)));
30254 (
MAN.
msg[ 1 ] == 0x00U )
30288 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 10)));
30314 (
MAN.
msg[ 0 ] & 0x07U ) == 0U
30489 int izzqqzz=((int)(
bitmapstruct.element6 |= (1 << 12)));
30490 ( void ) memset (
MAN.
time , 0 , 96 ) ;
30491 ( void ) memset (
MAN.
level , 0 , 96 ) ;
30492 ( void ) memset (
MAN.
msg , 0 , 4 ) ;
30510 int izzqqzz=((int)(
bitmapstruct.element6 |= (1 << 14)));
30537 fsk_adjust = fsk_adjust /
30560 int izzqqzz=((int)(
bitmapstruct.element6 |= (1 << 20)));
30595 int izzqqzz=((int)(
bitmapstruct.element6 |= (1 << 24)));
30598 bias_index = value ;
30621 #define qqqbranches 220 30622 #define QQQMAXMCDCSIZE 2 30626 #define ldra_sscanf 30642 #undef qqnull_params 30643 #define qqnull_params void 30645 #define qqzzidfield 1 30651 #define QQQFIXEDSIZE 30671 qqcptr = qqscan_str;
30673 while (qqcptr[0] ==
' ')
30679 if (qqcptr[0] ==
'-')
30685 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
30687 qqvalue = 10 * qqvalue;
30688 qqvalue = qqvalue + (qqcptr[0] -
'0');
30691 qqvalue = qqisign * qqvalue;
30717 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
30718 ldra_port_write (&ldra_buffer[0]);
30726 ldra_port_write(s);
30734 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
30735 ldra_port_write (&ldra_buffer[0]);
30743 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
30744 ldra_port_write (&ldra_buffer[0]);
30752 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
30753 ldra_port_write (&ldra_buffer[0]);
30872 static int branches_printed = 0;
30876 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
30877 ldra_port_write (&ldra_buffer[0]);
30878 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
30879 ldra_port_write (&ldra_buffer[0]);
30881 branches_printed += 8;
30901 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 30902 #define LASTELEMENT 30903 #include "man_59zbelem.def" bool GetDepthStatus(void)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void Calc_Auto_Bias(void)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void DRV_TMR_Close(DRV_HANDLE handle)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool DRV_USART0_TransmitBufferIsFull(void)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR3_Tasks(void)
static void Init_Manchester(void)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR0_PeriodValueSet(uint32_t value)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
void DRV_TMR3_Initialize(void)
void DRV_TMR2_CounterClear(void)
bool DRV_SPIn_ReceiverBufferIsFull(void)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
void DRV_IC_Stop(DRV_HANDLE handle)
void DRV_TMR3_PeriodValueSet(uint32_t value)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
static const uint8_t Xmit00[168]
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
static int man_59zqzqzq(int qqqi)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
static void DRV_TMR3_Open(void)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
void DRV_USART0_TasksTransmit(void)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
uint32_t DRV_TMR0_PeriodValueGet(void)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
static SYS_STATUS DRV_TMR1_Status(void)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Execute_Protocol_B(void)
void DRV_PMP0_Initialize(void)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
static uint32_t man_timer_count[100]
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
void DRV_TMR1_StopInIdleEnable(void)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
static void Execute_System(void)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
static void DRV_TMR2_Close(void)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
void DRV_ADC1_Close(void)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
static int man_59zqqzqz(qqnull_params)
void PLIB_USART_Disable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_DeInitialize(void)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
static void DRV_TMR2_Tasks(void)
DRV_USART_BAUD_SET_RESULT
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
void DRV_USART0_TasksError(void)
static void DRV_TMR4_Tasks(void)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void DRV_TMR0_Initialize(void)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void DRV_ADC0_Close(void)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void SYS_DEBUG_Message(const char *message)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
uint16_t DRV_IC0_Capture16BitDataRead(void)
static SYS_STATUS DRV_TMR0_Status(void)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
uint8_t jobQueueReserveSize
static SYS_STATUS DRV_TMR4_Status(void)
void Set_Status(uint8_t bitposn)
uint8_t Get_CRC_Value(void)
SYS_MODULE_INIT moduleInit
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
uint32_t DRV_TMR1_PeriodValueGet(void)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
static void Send_Mark(void)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR4_Close(void)
void DRV_IC0_Initialize(void)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static int qqqisinitialised
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR0_Open(void)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
static void Test_Manchester(void)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
static void DRV_TMR2_Open(void)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
INT_SOURCE txInterruptSource
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR1_DeInitialize(void)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
static MAN_STATES M_STATES
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
uint8_t Calc_CRC_Array(uint16_t Count, const uint8_t Bytes [])
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
static void Execute_Protocol_A(void)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
static void DRV_TMR1_Close(void)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void DRV_PMP0_ModeConfig(void)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
SPI_FRAME_PULSE_WIDTH framePulseWidth
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void DRV_TMR3_CounterClear(void)
bool spi_write_complete_flag
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
static MAN_PROCESS_STATES MTX_STATES
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
static SYS_STATUS DRV_TMR3_Status(void)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
static int man_59zqendz(int qqqi)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
void DRV_TMR1_Initialize(void)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void DRV_PMP0_Write(uint8_t data)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
static void qqoutput(FILEPOINT char *s, int i)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
static void DRV_TMR0_Tasks(void)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
static void Send_Space(void)
void DRV_TMR4_StopInIdleDisable(void)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_TYPE bufferType
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
ldra_void_function qqqaccumupload[QQQnumfil]
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_Close(const DRV_HANDLE handle)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
bool Valid_Command(uchar8_t msg)
static int qqqqbmselwidth
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
static unsigned char qqqzzglobflag
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
void APP_Initialize(void)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
void DRV_TMR_Stop(DRV_HANDLE handle)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
#define DRV_IC_Open(drvIndex, intent)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool DRV_TMR_Start(DRV_HANDLE handle)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
static void DRV_TMR0_Close(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool SYS_DMA_IsBusy(void)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void(* ldra_void_function)()
uint32_t DRV_TMR3_CounterValueGet(void)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void qqqtotalupload(void)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
static bool Check_Manchester(void)
SPI_FRAME_PULSE_EDGE framePulseEdge
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
void Prepare_Return_B(uint8_t byt [])
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
uint32_t DRV_TMR0_CounterValueGet(void)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
void DRV_TMR3_CounterValueSet(uint32_t value)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
static void qqqbitmapreset(qqnull_params)
DRV_SPI_BUFFER_HANDLE bufferHandle2
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void DRV_TMR3_StopInIdleDisable(void)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
struct _DRV_SPI_INIT DRV_SPI_INIT
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool process_complete_flag
static void MAN_PROCESS_Tasks(void)
uintptr_t DRV_USART_BUFFER_HANDLE
void SYS_DEBUG_Print(const char *format,...)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
static void Send_Message_Tasks(void)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
static MAN_RX_STATES MRX_STATES
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
static void DRV_TMR4_Open(void)
uint8_t Calc_CRC_Uplink(uint16_t Count, const uint8_t Bytes [])
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_USART_Enable(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
uint32_t DRV_TMR4_PeriodValueGet(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool DRV_TMR4_Start(void)
CLK_BUSES_PERIPHERAL spiClk
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void DRV_TMR1_StopInIdleDisable(void)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
static void Init_WL_CPS(void)
void Generate_Sine_Wave_Data(float32_t NoOfTicks)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
void DRV_ADC_DeInitialize(void)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
static int qqqstructzzopen
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_IC0_Capture32BitDataRead(void)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
#define DRV_IC_Close(handle)
static void DRV_TMR2_DeInitialize(void)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
static int man_59zscanf(char *qqscan_str)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
static void Init_FSK(void)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void DRV_TMR4_CounterValueSet(uint32_t value)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
void DRV_TMR4_CounterClear(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
uint32_t SYS_DMA_ChannelCRCGet(void)
void Set_Bias(uint8_t value)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
static struct bitmapstruct_t bitmapstruct
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void DRV_TMR0_CounterValueSet(uint32_t value)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
bool DRV_TMR3_Start(void)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
static const uint8_t Xmit11[312]
static void qqoutput2(FILEPOINT char *s, int i, int j)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t DRV_USART0_ReadByte(void)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_BAUD_SET_RESULT
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART0_Close(void)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
static void Read_WL_CPS_V_I(void)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void Prepare_Dwn_Msg(uint8_t Identifier, uint8_t Cmd, uint8_t Msg_Length)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void Check_WL_CPS_Over_Current(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void DRV_ADC_Initialize(void)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
void Calc_CRC(uint16_t nbits, uint8_t thebits)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
static void Flush_Buffer_Manchester(void)
void DRV_TMR4_Initialize(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
uint32_t DRV_TMR4_CounterValueGet(void)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
SYS_ERROR_LEVEL gblErrLvl
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void Clear_Status(uint8_t bitposn)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
static void DRV_TMR0_DeInitialize(void)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
MAN_PROCESS_STATES Process_state
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void Adjust_WL_CPS_Voltage(uint8_t target)
static void qqqqinitialise(int ii)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void DRV_TMR4_StopInIdleEnable(void)
static const uint8_t biasval[48U]
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
bool DRV_TMR1_Start(void)
static void SPI_1_EventHandler(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_USART_LINE_CONTROL_SET_RESULT
static void DRV_TMR1_Tasks(void)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
static void DRV_TMR3_Close(void)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void DRV_TMR2_Initialize(void)
SPI_AUDIO_PROTOCOL audioProtocolMode
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
DRV_SPI_CLOCK_MODE clockMode
static void Decode_Manchester(void)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
void DRV_USART0_Deinitialize(void)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR2_Start(void)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
INT_SOURCE rxInterruptSource
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
void DRV_TMR2_StopInIdleDisable(void)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_TMR2_StopInIdleEnable(void)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
INT_SOURCE errInterruptSource
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART0_WriteByte(const uint8_t byte)
void DRV_TMR0_CounterClear(void)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR3_PeriodValueGet(void)
void DRV_TMR1_CounterValueSet(uint32_t value)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle
void DRV_TMR0_StopInIdleEnable(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR3_StopInIdleEnable(void)
bool DRV_IC0_BufferIsEmpty(void)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
static float32_t Calc_Fsk_Scaling(void)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void DRV_TMR2_CounterValueSet(uint32_t value)
SYS_DMA_CHANNEL_IGNORE_MATCH
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
uint32_t DRV_TMR2_CounterValueGet(void)
DRV_SPI_TASK_MODE taskMode
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
void Set_WL_CPS_CurrentLimit(uint8_t value)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
static void Package_Manchester(void)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void Reset_CRC_Value(void)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
static void qqqupload(qqnull_params)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
void DRV_TMR1_CounterClear(void)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
void SYS_DMA_Suspend(void)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_Initialize()
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
bool b_command_complete_flag
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
SPI_FRAME_SYNC_PULSE frameSyncPulse
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
static void DRV_TMR1_Open(void)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
bool DRV_TMR0_Start(void)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR1_PeriodValueSet(uint32_t value)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
SYS_DMA_CHANNEL_CHAIN_PRIO
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
void SYS_DMA_Resume(void)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
uint32_t DRV_TMR1_CounterValueGet(void)